In an ADSL (Asymmetric Digital Subscriber Line) modem, power consumption is a very important factor, especially on the Central Office (CO) side. If the power consumption can be lowered, the number of lines per line card can be increased without additional cooling. One of the large power consumers in an ADSL modem is the Line Driver (LD). The power efficiency of standard ADSL line drivers is quite low.
In an attempt to increase the power efficiency of line drivers, new methods of designing the line drivers have been investigated.
One of these methods involves using a class D amplifier. The output stage of the class D amplifier drives the modulated input signal onto the line through a low pass LC filter which demodulates the signal into a continuous ADSL signal.
Today, various techniques are used to implement class D amplifiers, but most use the same inverter-type of switching output stage. However, it is expensive to manufacture high-voltage components such as those needed to obtain the voltage levels required by ADSL. Thus, it would be advantageous if low-voltage components could be used instead. Also, solutions to date for class D implementations are designed for audio band frequencies (up to 4 kHz). DSL applications use much higher frequencies (several MHz). This places tougher requirements on speed in the class D implementation.
In ADSL, the maximum voltage amplitude needed on the line is 30 V peak-to-peak at the CO side with a PAR (Peak to Average Ratio) of 4.5. If a transformer is used, the voltage requirements on the output stage can be reduced. However, the output stage should still be able to handle relatively high voltages. The transformer turn ratio should be kept as low as possible since a high transformer turn ratio will increase the required output current and degrade the receive path. Higher currents lead to larger output transistors and hence larger power consumption in the drivers.
In a manner known per se, the class D output stage comprises an NMOS transistor and a PMOS transistor that must not be on at the same time. If both transistors were on at the same time, a high current would be obtained through the transistors. This high current would destroy the output stage or for shorter duration lead to power loss.
In order to ensure that the NMOS and PMOS transistors are not on at the same time, a time delay is introduced between the turn-off time of the NMOS transistor and the turn-on time of the PMOS transistor and vice versa. This so-called deadtime should be as short as possible since it leads to distortion.
The resistance of the output transistors when on should be as low as possible in order to reduce the power loss.
Since the ADSL line driver market is very competitive, small die sizes and relatively inexpensive manufacturing processes are important.